Some conventional clock generator circuits include a pair of NOR circuits cross-coupled to each other, which serve as an R-S flip-flop. Such a conventional clock generator circuit generates two non-overlapping clock signals φ1 and φ2 opposite in phase to each other. In this conventional circuit, when an inverter is connected to the output terminal of each of the NOR circuits, two inverted clock signals of φ1 and φ2 are also obtained. Thus, the clock generator circuit associated with such inverters generates two pairs of clock signals (φ1 and φ2 and inverted clock signals of φ1 and φ2). To extend this two phase non-overlapping clock generator with more phases of clock signals, this circuit can be cascaded to accept multiple signals accordingly.
However, in the above-mentioned circuit, the sequence of the clock signals are hardwired and cannot be reconfigured without re-routing the wires unless there are multiplexers introduced in the signal path as illustrated in FIG. 2. Also, due to fluctuation in manufacture, the delay time of each of the inverters is fluctuated. At worst, this delay time is so long that the clock signal φ1 may be overlapped with the clock signal φ2.
In another conventional clock generator circuit, a clock input is provided to a level shifter and clock buffer. The output of the buffer is provided to a divide-by-two circuit, which divides the frequency of clock down to a rising-edge clock level and a falling-edge clock level. These clock levels are input to a clock driver that generates clock signals φ1 and φ2. However, this conventional clock generator circuit has the fixed sequence when it is extended to more than two phases of clock signals. Also, it suffers from clock delay due to the buffering and intermediate logic.
One implementation of these conventional clock generator circuits is in an analog-to-digital converter circuit. For example, a conventional analog-to-digital converter circuit may include a clock generator circuit having fixed timing sequences and utilizing a four phase signal generator. In this clock generator circuit, two pairs of clock signals are generated by using a reference clock signal. Moreover, this conventional clock generator circuit generates a pair of clock signals that are opposite in phase to each other and which do not overlapped with another pair of clock signals opposite in phase to each other. Another possible implementation is using a cascaded multi-phase non-overlapping clock generator, but it does not allow the changing of the sequence of the clock signals unless there is a reconfigurable signal path as explained below.
FIG. 2 illustrates a prior art circuit and method of generating non-overlapping clock signals with reference to other signals that can generate multi-phase non-overlapping signal generator with n number of (n−1)→1 multiplexers and has a delay cell for each signal generator. As illustrated in FIG. 2, each multiplexer (210, 240, 270) receives n−1 phase signals out of the n phase signals (ph1 through ph(n)) to make the reconfigurable clock signal path to allow reconfigurable clock sequence.
As further illustrated in FIG. 2, multiplexer 210 selects one of the signals (ph2 through ph(n)) based upon received selection signals (C1-CM); multiplexer 240 selects one of the signals (ph1 and ph3 through ph(n)) based upon received selection signals (C1-CM); and multiplexer 270 selects one of the signals (ph1 through ph(n−1)) based upon received selection signals (C1-CM). Thus, each multiplexer receives a subset of the n phase signals (ph1 through ph(n)).
The selected signal is input to a NOR circuit (220, 250, 280). For example, the selected signal from multiplexer 210 is input to a NOR circuit 220; the selected signal from multiplexer 240 is input to a NOR circuit 250; and the selected signal from multiplexer 270 is input to a NOR circuit 280.
The selected signals are NOR'ed with an input signal (In1, In2, . . . , In(n)). For example, the selected signal from multiplexer 210 is NOR'ed with input signal In1; the selected signal from multiplexer 240 is NOR'ed with input signal In2; and the selected signal from multiplexer 270 is NOR'ed with input signal In(n). To generate the proper delay, the NOR'ed signals are input to a delay cell (230, 260, 290) with gate delays.
The prior art circuit of FIG. 2 generates non-overlapping signals, which are dependent upon other signals. More specifically, the prior art circuit of FIG. 2 generates non-overlapping signals, which are dependent upon the delay cells between the input signal (In1, In2, . . . , In(n)) path and output clock signals (ph1 through ph(n)).
Moreover, the prior art circuit of FIG. 2 may require large area overhead from the multiplexers and also the replica delays for each signal to accommodate any changes in the sequence of the clock signals. Lastly, the prior art circuit of FIG. 2 cannot generate non-overlapping signals wherein the delays in the rising and falling edges of the signals are independent of each other.
Therefore, it is desirable to provide a clock generation circuit which generates non-overlapping signals. Moreover, it is desirable to provide a clock generation circuit which generates non-overlapping signals that are not dependent upon other signals. Also, it is desirable to provide a clock generation circuit which generates non-overlapping signals without utilizing a large area of the chip. Lastly, it is desirable to provide a clock generation circuit which generates non-overlapping signals wherein the delays in the rising and falling edges of the signals are independent of each other.